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1 ps8450d 03/06/08 features ? all output pair skew <100ps typical (250 max.) ? 3.75 mhz to 80 mhz output operation ? user-selectable output functions ? selectable skew to 18ns ? inverted and non-inverted ? operation at ? and ? input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz, x4 operation) ? zero input-to-output delay ? 50% duty-cycle outputs ? lvttl outputs drive 50-ohm terminated lines ? operates from a single 3.3v supply ? low operating current ? available in 32-pin plcc (j) package ? jitter < 200ps peak-to-peak (< 25ps rms) description pi6c3991 offers selectable control over system clock functions. these multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-perfor- mance computer systems. eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated trans- mission lines with impedances as low as 50 ohms while delivering minimal and specified output skews and full-swing logic levels (lvttl). each output can be hardwired to one of nine skews or function configurations. delay increments of 0.7ns to 1.5ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows external load and transmission line delay effects to be canceled. the user can create output-to-output skew up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. this feature allows flexibility and simplifies system timing distribution design for complex high-speed systems. logic block diagram pin configuration 1q 0 1q 1 1f0 1f1 2q 0 2q 1 2f0 2f1 3q 0 3q 1 3f0 3f1 4q 0 4q 1 4f0 4f1 select inputs (three level) matrix select skew test filter phase freq. det fb r ef vco and time unit generator fs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer superclock ? 2f0 gnd 1f1 1f0 v cc n 1q0 1q1 gnd gnd 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3q1 3q0 v ccn fb v ccn 2q1 2q0 3f0 fs v cc q ref gnd tes t 2f1 4321323130 14 15 16 17 18 19 20 32-pin j
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2 ps8450d 11/12/08 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? pin descriptions e m a n l a n g i so / in o i t p i r c s e d f e ri . d e r u s a e m s i n o i t a i r a v l a n o i t c n u f l l a h c i h w t s n i a g a g n i m i t d n a y c n e u q e r f e h t s e i l p p u s t u p n i s i h t . t u p n i y c n e u q e r f e c n e r e f e r b fi ) s t u p t u o t h g i e e h t f o e n o o t d e t c e n n o c y l l a c i p y t ( t u p n i k c a b d e e f l l p s fi . 1 e l b a t e e s . t c e l e s e g n a r y c n e u q e r f l e v e l - e e r h t 1 f 1 , 0 f 1i . 2 e l b a t e e s . ) 1 q 1 , 0 q 1 ( 1 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 1 f 2 , 0 f 2i . 2 e l b a t e e s . ) 1 q 2 , 0 q 2 ( 2 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 1 f 3 , 0 f 3i . 2 e l b a t e e s . ) 1 q 3 , 0 q 3 ( 3 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t 1 f 4 , 0 f 4i . 2 e l b a t e e s . ) 1 q 4 , 0 q 4 ( 4 r i a p t u p t u o r o f s t u p n i t c e l e s n o i t c n u f l e v e l - e e r h t t s e ti s n o i t p i r c s e d m a r g a i d k c o l b e h t r e d n u n o i t c e s e d o m t s e t e e s . t c e l e s l e v e l - e e r h t 1 q 1 , 0 q 1o 2 e l b a t e e s . 1 r i a p t u p t u o 1 q 2 , 0 q 2o 2 e l b a t e e s . 2 r i a p t u p t u o 1 q 3 , 0 q 3o 2 e l b a t e e s . 3 r i a p t u p t u o 1 q 4 , 0 q 4o 2 e l b a t e e s . 4 r i a p t u p t u o v n c c r w ps r e v i r d t u p t u o r o f y l p p u s r e w o p v q c c r w py r t i u c r i c l a n r e t n i r o f y l p p u s r e w o p d n gr w pd n u o r g s f ) 2 , 1 ( f m o n ) z h m ( t u = = n e r e h w e t a m i x o r p p a t a ) z h m ( . q e r f t h c i h w u s n 0 . 1 = . n i m. x a m w o l5 10 34 47 . 2 2 d i m5 20 56 25 . 8 3 h g i h0 40 86 15 . 2 6 table 1. frequency range select and t u calculation (1) 1 f nom n s t c e l e s n o i t c n u fs n o i t c n u f t u p t u o , 1 f 2 , 1 f 1 1 f 4 , 1 f 3 , 0 f 2 , 0 f 1 0 f 4 , 0 f 3 , 1 q 1 , 0 q 1 1 q 2 , 0 q 2 1 q 3 , 0 q 31 q 4 , 0 q 4 w o lw o lt 4 ? u 2 y b e d i v i d2 y b e d i v i d w o ld i mt 3 ? u t 6 ? u t 6 ? u w o lh g i ht 2 ? u t 4 ? u t 4 ? u d i mw o lt 1 ? u t 2 ? u t 2 ? u d i md i mt 0 u t 0 u t 0 u d i mh g i ht 1 + u t 2 + u t 2 + u h g i hw o lt 2 + u t 4 + u t 4 + u h g i hd i mt 3 + u t 6 + u t 6 + u h g i hh g i ht 4 + u 4 y b e d i v i dd e t r e v n i table 2. programmable skew configurations (1) notes: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ?normal? operating frequency (f nom ) and time unit generator (see logic block diagram). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see table 2). the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for a frequency multiplication by using a divided output as the fb input.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? 3 ps8450d 1 1/12/08 t 0 ?6 t u t 0 ?5 t u t 0 ?4 t u t 0 ?3 t u t 0 ?2 t u t 0 ?1 t u t 0 t 0 +1 t u t 0 +2 t u t 0 +3 t u t 0 +4 t u t 0 +5 t u t 0 +6 t u fb input ref input (n/a) hh invert (n/a) ll/hh divided ( n/a) lm ?6t u ll lh ?4t u lm (n/a) ?3t u lh ml ?2t u ml (n/a) ?1t u mm mm 0t u mh (n/a) +1t u hl mh +2t u hm (n/a) +3t u hh hl +4t u ( n/a) hm +6t u 1fx 2fx 3fx 4fx figure 1. typical outputs with fb connected to a zero-skew output (3) note: 3. fb connected to an output selected for "zero" skew (ie., xf1 = xf0 = mid). block diagram description phase frequency detector and filter these two blocks accept input signals from the reference frequency (ref) input and the feedback (fb) input and generate correction information to control the frequency of the voltage-controlled oscillator (vco). these blocks, along with the vco, form a phase- locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew mix matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the level of the fs pin as shown in table 1. skew select matrix the skew select matrix is comprised of four independent sections. each section has two low-skew, high-fanout drivers (xq0, xq1), and two corresponding three-level function select (xf0, xf1) inputs. table 2 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. e g n a re r u t a r e p m e t t n e i b m av c c l a i c r e m m o cc 0 7 + o t c 0% 0 1 v 3 . 3 l a i r t s u d n ic 5 8 + o t c 0 4 ?% 0 1 v 3 . 3 test mode the test input is a three-level input. in normal system operation, this pin is connected to ground, allowing the pi6c3991 to operate as explained briefly above (for testing purposes, any of the three level inputs can have a removable jumper to ground, or be tied low through a 100 ohm resistor. this will allow an external tester to change the state of these pins.) if the test input is forced to its mid or high state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to ref will directly control all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operation (test tied low). all outputs will function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. storage temperature ...................................... ?65c to +150c ambient temperature with power applied ................................................. ?55c to +125c supply voltage to ground potential .................. ?0.5v to +7.0v dc input voltage ............................................... ?0.5v to +7.0v output current into outputs (low) ............................... 64ma static discharge voltage ............................................... >2001v (per mil-std-883, method 3015) latch-up current ......................................................... >200ma maximum ratings operating range
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 4 ps8450d 11/12/08 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. x a ms t i n u v h o e g a t l o v h g i h t u p t u ov c c i , . n i m = h o a m 2 1 ? =4 . 2 v v l o e g a t l o v w o l t u p t u ov c c i , . n i m = l o a m 5 3 =5 4 . 0 v h i b f & f e r ( e g a t l o v h g i h t u p n i ) y l n o s t u p n i 0 . 2v c c v l i s t u p n i b f & f e r ( e g a t l o v w o l t u p n i ) y l n o 5 . 0 ?8 . 0 v h h i e g a t l o v h g i h t u p n i l e v e l - e e r h t ) n f x , s f , t s e t ( ) 4 ( . n i m v c c . x a mv 7 8 . 0 c c v c c v m m i e g a t l o v d i m t u p n i l e v e l - e e r h t ) n f x , s f , t s e t ( ) 4 ( . n i m v c c . x a mv 7 4 . 0 c c v 3 5 . 0 c c v l l i e g a t l o v w o l t u p n i l e v e l - e e r h t ) n f x , s f , t s e t ( ) 4 ( . n i m v c c . x a m0 . 0v 3 1 . 0 c c i h i t n e r r u c e g a k a e l h g i h t u p n i ) y l n o s t u p n i b f & f e r ( v c c v , . x a m = n i . x a m =0 2 a i l i t n e r r u c e g a k a e l w o l t u p n i ) y l n o s t u p n i b f & f e r ( v c c v , . x a m = n i v 4 . 0 =0 2 ? i h h i ) n f x , s f , t s e t ( t n e r r u c h g i h t u p n iv n i v = c c 0 0 2 i m m i ) n f x , s f , t s e t ( t n e r r u c d i m t u p n iv n i v = c c 2 /0 5 ?0 5 i l l i ) n f x , s f , t s e t ( t n e r r u c w o l t u p n iv n i= d n g0 0 2 ? i s o t n e r r u c t i u c r i c t r o h s ) 5 ( v c c v , . x a m = t u o ) y l n o c 5 2 ( d n g =0 0 2 ? a m i q c c l a n r e t n i y b d e s u t n e r r u c g n i t a r e p o y r t i u c r i c v n c c v = q c c , . x a m = n e p o s t c e l e s t u p n i l l a l ' m o c5 9 d n i / l i m0 0 1a m i n c c r i a p t u p t u o r e p t n e r r u c r e f f u b t u p t u ov n c c v = q c c , . x a m = i t u o a m 0 = f , n e p o s t c e l e s t u p n i l l a x a m 9 1a m d pr i a p t u p t u o r e p n o i t a p i s s i d r e w o pv n c c v = q c c , . x a m = i t u o a m 0 = f , n e p o s t c e l e s t u p n i l l a x a m 4 0 1w m electrical characteristics (over the operating range) notes: 4. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. 5. pi6c3991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room temperature only. 6. applies to ref and fb inputs only. tested initially and after any design or process changes that may affect these parameters. r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. x a ms t i n u c n i e c n a t i c a p a c t u p n it a v , z h m 1 = f , c 5 2 = c c v 3 . 3 =0 1f p capacitance (6)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? 5 ps8450d 1 1/12/08 r e t e m a r a pn o i t p i r c s e d 2 - 1 9 9 3 c 6 i p5 - 1 9 9 3 c 6 i p1 9 9 3 c 6 i p . n i m. p y t. x a m. n i m. p y t. x a m. n i m. p y t. x a ms t i n u f m o n g n i t a r e p o y c n e u q e r f k c o l c z h m n i w o l = s f ) 2 , 1 ( 5 10 35 10 35 10 3 z h m d i m = s f ) 2 , 1 ( 5 20 55 20 55 20 5 h g i h = s f ) 2 , 1 ( 0 40 80 40 80 40 8 t h w p r h g i h h t d i w e s l u p f e r0 . 50 . 50 . 5 s n t l w p r w o l h t d i w e s l u p f e r0 . 50 . 50 . 5 t u t i n u w e k s e l b a m m a r g o r p 1 e l b a t e e s1 e l b a t e e s1 e l b a t e e s t r p w e k s ) 1 q x , 0 q x ( w e k s r i a p - d e h c t a m t u p t u o o r e z ) 0 1 , 9 ( 5 0 . 02 . 01 . 05 2 . 01 . 05 2 . 0 s n t 0 w e k s ) s t u p t u o l l a ( w e k s t u p t u o o r e z ) 1 1 , 9 ( 1 . 05 2 . 05 2 . 05 . 03 . 05 7 . 0 t 1 w e k s ) s t u p t u o s s a l c e m a s , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 3 1 , 9 ( 1 . 05 . 06 . 07 . 06 . 00 . 1 t 2 w e k s ) d e d i v i d - d e d i v i d , d e t r e v n i - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 3 1 , 9 ( 5 . 00 . 15 . 00 . 10 . 15 . 1 t 3 w e k s ) s t u p t u o s s a l c t n e r e f f i d , l l a f - l l a f , e s i r - e s i r ( w e k s t u p t u o ) 3 1 , 9 ( 5 2 . 05 . 05 . 07 . 07 . 02 . 1 t 4 w e k s d e t r e v n i - d e d i v i d , d e d i v i d - l a n i m o n , l l a f - e s i r ( w e k s t u p t u o ) 3 1 , 9 ( 5 . 09 . 05 . 00 . 12 . 17 . 1 t v e d w e k d e c i v e d - o t - e c i v e d ) 4 1 , 8 ( 5 2 . 15 2 . 15 6 . 1 t d p e s i r b f o t e s i r f e r , y a l e d n o i t a g a p o r p5 2 . 0 ?0 . 05 2 . 0 +5 . 0 ?0 . 05 . 0 +7 . 0 ?0 . 07 . 0 + t v c d o n o i t a i r a v e l c y c y t u d t u p t u o ) 5 1 ( 5 6 . 0 ?0 . 05 6 . 0 +0 . 1 ?0 . 00 . 1 +2 . 1 ?0 . 02 . 1 + t h w p % 0 5 m o r f n o i t a i v e d e m i t h g i h t u p t u o ) 6 1 ( 0 . 25 . 23 t l w p % 0 5 m o r f n o i t a i v e d e m i t w o l t u p t u o ) 6 1 ( 5 . 10 . 35 . 3 t e s i r o e m i t e s i r t u p t u o ) 7 1 , 6 1 ( 5 1 . 00 . 12 . 15 1 . 00 . 15 . 15 1 . 05 . 15 . 2 t l l a f o e m i t l l a f t u p t u o ) 7 1 , 6 1 ( 5 1 . 00 . 12 . 15 1 . 00 . 15 . 15 1 . 05 . 15 . 2 t k c o l e m i t k c o l l l p ) 8 1 ( 5 . 05 . 05 . 0s m t r j e l c y c - o t - e l c y c r e t t i j t u p t u o s m r ) 8 ( 5 25 25 2 s p k a e p - o t - k a e p ) 8 ( 0 0 20 0 20 0 2 switching characteristics pi6c3991 (over the operating range) (2,7) notes: 7. test measurement levels for the pi6c3991 are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 8. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these paramet ers. 9. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 30pf and terminated with 50 ohm to v cc /2. 10. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 11. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 12. c l = 0pf. for c l = 30pf, t skew0 = 0.35ns. 13. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 14. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.) 15. t odcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. 16. specified with outputs loaded with 30pf for the pi6c3991 and pi6c3991-5 devices. devices are terminated through 50 ohm to v cc / 2. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 17. t orise and t ofall measured between 0.8v and 2.0v. 18. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 6 ps8450d 11/12/08 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? ac timing diagrams t ref t rpwh t odcv t skewpr t skew0, 1 t skew3,4 t skew3,4 t skew3,4 t skew2,4 t skew1,3,4 t skewpr t skew0, 1 t pd t odcv t rpwl t j r ref fb q other q inverted q r ef divided by 2 r ef divided by 4 t skew2 t skew2 v cc 1ns 1ns 3.0v 2.0v vth=1.5v 0.8v 0v r1 r1=100 r2=100 c l =30pf (includes fixture and probe capacitance) r2 c l ttl input test waveform ttl ac test load ac test loads and waveforms
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? 7 ps8450d 1 1/12/08 operational mode descriptions figure 2. zero-skew and/or zero-delay clock driver figure 2 shows the superclock configured as a zero-skew clock buffer. in this mode the pi6c3991 can be used as the basis for a low- skew clock distribution tree. when all of the function select inputs (xf0, xf1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. the fb input fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 s ystem clock ref load load load load l1 l2 l3 l4 z 0 z 0 z 0 z 0 length: l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 system clock ref load load load load l1 l2 l3 l4 z 0 z 0 z 0 z 0 length: l1 = l2, l3 < l2 by 6", l4 > l2 by 6" figure 3. programmable skew clock driver can be tied to any output in this configuration and the operating frequency range is selected with the fs pin. the low-skew specifi- cation, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohm), allows efficient printed circuit board design.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 8 ps8450d 11/12/08 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? figure 3 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the superclock can be programmed to stagger the timing of its outputs. the four groups of output pairs can each be programmed to different output timing. skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. in this configuration the 4q0 output is fed back to fb and configured for zero skew. the other three pairs of outputs are programmed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. in this illustration the fb input is connected to an output with 0ns skew (xf1, xf0 = mid) selected. the internal pll synchronizes the fb and ref inputs and aligns their rising edges to insure that all outputs have precise phase alignment. clock skews can be advanced by 6 time units (t u ) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ?zero skew?, +t u , and ?t u are defined relative to output groups, and since the pll aligns the rising edges of ref and fb, it is possible to create wider output skews by proper selection of the xfn inputs. for example a +10 t u between ref and 3qx can be achieved by connect- ing 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 t u and 3qx skews to +6 t u , a total of +10 t u skew is realized). many other configurations can be realized by skewing both the output used as the fb input and skewing the other outputs. figure 4. inverted output connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref figure 4 shows an example of the invert function of the superclock. in this example the 4q0 output used as the fb input is programmed for invert (4f0 = 4f1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this causes the 1q, 2q, and 3q outputs to become the ?inverted? outputs with respect to the ref input. by selecting which output is connect to fb, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. the correct configura-tion would be determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs can also be skewed to compensate for varying trace delays independent of inver-sion on 4q. figure 5. frequency multiplier with skew connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref 20 mhz 40 mhz 20 mhz 80 mhz figure 5 illustrates the superclock configured as a clock multiplier. the 3q0 output is programmed to divide by four and is fed back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, which results in a 40 mhz waveform at these outputs. note that the rising edges of 4qx and 3qx outputs are aligned. the 2q0, 2q1, 1q0, and 1q1 outputs run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80 mhz operation because that is the frequency of the fastest output.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? 9 ps8450d 1 1/12/08 figure 6. frequency divider connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref 20 mhz 10 mhz 5 mhz 20 mhz figure 6 demonstrates the superclock in a clock divider application. 2q0 is fed back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the rising edges of the 4qx and 3qx outputs are aligned. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15 to 30 mhz range since the highest frequency output is running at 20 mhz. figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output allows the system designer to clock different sub-systems on opposite edges, without suffering from the pulse asymmetry typical of non- ideal loading. this function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. the divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, an external divider would need to be add-ed, and the propagation delay of the divider would add to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, allow the superclock to multiply the clock rate at the ref input by either two or four. this mode will enable the designer to distribute a low- frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. the superclock can perform all of the functions described above at the same time. it can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. figure 7. multi-function clock driver fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 20 mhz distribution clock ref load load load load z 0 z 0 z 0 z 0 80 mhz inverted 20 mhz 80 mhz zero skew 80 mhz skewed ?3.125ns (?4t u )
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 10 ps8450d 11/12/08 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? figure 8. board-to-board clock distribution figure 8 shows the pi6c3991 connected in series to construct a zero skew clock distribution tree between boards. delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero- fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 s ystem c lock ref load z 0 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 test 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 load z 0 load load load z 0 z 0 l1 l2 l3 l4 delay clock tree. cascaded clock buffers will accumulate low-fre- quency jitter because of the non-ideal filtering characteristics of the pll filter. it is recommended that not more than two clock buffers be connected in series.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c3991 3.3v high-speed, low-voltage programmable skew clock buffer - superclock ? 11 ps8450d 1 1/12/08 pericom semiconductor corporation ? 1-800-435-2336 ? http://www.pericom.com package diagram - 32-pin plcc (j) ) s p ( y c a r u c c ae d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o 0 5 7e j - 1 9 9 3 c 6 i p2 3 jr e i r r a c p i h c d e d a e l c i t s a l p n i p - 2 3l a i c r e m m o c 0 5 2e j 2 - 1 9 9 3 c 6 i p2 3 jr e i r r a c p i h c d e d a e l c i t s a l p n i p - 2 3l a i c r e m m o c 0 0 5e j 5 - 1 9 9 3 c 6 i p2 3 jr e i r r a c p i h c d e d a e l c i t s a l p n i p - 2 3l a i c r e m m o c ordering information notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free & green ? x suffix = tape/reel

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